1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit that generates a spread spectrum clock, and a communication device using the same.
2. Description of Related Art
A spread spectrum clock (SSC) signal has been generally employed in order to suppress occurrence of EMI (Electro Magnetic Interference) by electronic devices. For example, an SSC is generated by modulating frequency of a clock signal generated by a PLL circuit or the like in accordance with a predetermined modulation frequency and modulation degree. Patent documents 1 to 5 listed below disclose a device that generates an SSC.
Patent document 1: Japanese Unexamined Patent Application Publication No. 2006-166049
Patent document 2: U.S. Pat. No. 6888412
Patent document 3: Japanese Patent No. 4074166
Patent document 4: Japanese Unexamined Patent Application Publication No. 2007-6121
Patent document 5: Japanese Unexamined Patent Application Publication No. 2006-211479
An SSC generation device disclosed in the patent document 1 generates, by means of a phase interpolator, a frequency-modulated SSC by advancing or retarding phase of an output clock signal that is generated by a clock generating circuit such as a PLL circuit or the like.
On the other hand, the patent documents 2 to 5 disclose a PLL circuit that includes an SSC generation function. Among them, a PLL circuit disclosed in the patent documents 2 and 3 includes a phase interpolator arranged on a feedback path that supplies an output clock signal of a voltage controlled oscillator (VCO) to a phase comparator or a phase and frequency comparator for phase comparison with a reference signal. An output clock signal of a VCO is frequency-modulated by periodically advancing or retarding the phase of the output clock signal by the phase interpolator, to thereby obtain the SSC Further, a PLL circuit disclosed in the patent document 4 generates an SSC by periodically changing a delay amount applied to a feedback clock signal by a delay circuit arranged on a feedback path of the PLL circuit. Further, a PLL circuit disclosed in the patent document 5 generates an SSC by periodically changing a frequency dividing ratio of a frequency divider arranged on a feedback path of the PLL circuit.
When the output of the clock generating circuit is frequency-modulated by the method disclosed in the patent document 1, a jitter of the SSC tends to be made large because a high frequency jitter component that is produced by phase control of the phase interpolator is superimposed on the SSC. On the other hand, the PLL circuit disclosed in the patent documents 2 and 3 periodically increases or decreases the control voltage of the VCO by arranging the phase interpolator, which is the component for performing frequency modulation, on the feedback path, and frequency-modulates the output clock signal of the VCO by the control voltage that is periodically fluctuated. Accordingly, as the high frequency jitter component that is produced by phase control of the phase interpolator decays by closed loop frequency characteristics (low-pass filter characteristics) of the PLL, the PLL circuit disclosed in the patent documents 2 and 3 may improve the jitter characteristics of the SSC.